Conserving resources, including energy, has become a pre-eminent objective in today's world. Manufacturers of ICs are sensitive to the need to improve the energy efficiency of their products. Those skilled in the pertinent art are aware that various measures may be taken in an electronic circuit to reduce its power consumption. One measure is to use cells (i.e., logic elements including devices, e.g., transistors) that leak less current when turned off. Another measure is to use a lower voltage to drive the cells. Unfortunately, using lower leakage current cells or lower drive voltages almost always reduces the speed at which signals propagate through the circuit. Consequently, the circuit may not operate as fast as needed or desired.
Area and yield are also important considerations in circuit design. IC fabrication cost generally decreases as IC substrate (“die”) size decreases. Increasing yield means decreasing scrap, which by definition reduces overall IC fabrication cost.
Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer logic (RTL representation) representation of the functional circuit design, generate a “netlist” from the RTL representation, and synthesize a layout from the netlists. Synthesis of the layout involves simulating the operation of the circuit and determining where cells should be placed and where the interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, determine its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern ICs, particularly very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
One such EDA tool performs timing signoff. Timing signoff is one of the last steps in the IC design process and ensures that signal propagation speed in a newly-designed circuit is such that the circuit will operate as intended. Signals that propagate too slowly through the circuit cause setup violations; signals that propagate too quickly through the circuit cause hold violations. Setup or hold violations corrupt the flow of logic through the logic of the circuit and give rise to functional errors.
Timing signoff is performed with highly accurate models of the circuit under multiple sets of assumptions regarding expected variations, called “PVT corners.” Process-voltage-temperature (PVT) PVT corners are based on assumptions regarding variations in device operation, drive voltage and operating temperature. Resistance-capacitance (R, C, or RC) PVT corners are based on assumptions regarding variations in one or both of interconnect resistance and capacitance from one IC to another. Conventional timing signoff identifies setup and hold violations in a “slow” PVT corner (in which process variations are assumed to yield relatively slow-switching devices, and drive voltage and operating temperature are such that device switching speeds are their slowest) and a “worst” RC corner (in which process variations are assumed to yield interconnects having relatively high resistance and capacitance). Conventional timing signoff also identifies hold violations in a “fast” PVT corner (in which process variations are assumed to yield relatively fast-switching devices, and drive voltage and operating temperature are such that device switching speeds are their fastest) and a “best” RC corner (in which process variations are assumed to yield interconnects having relatively low resistance and capacitance). Conventional signoff timing also takes on-chip variations (OCV), which are process variations occurring over the area of a given IC, into account using statistical methods. The fast PVT and best RC corner are sometimes jointly referred to as a fast-fast (FF) or best-case fast (BCF) corner, and the slow PVT and worst RC corner are sometimes jointly referred to as a slow-slow (SS) or worst-case slow (WCS) corner.
Thus a fundamental tradeoff exists among speed and power consumption. Further considerations involve speed, power consumption, area and yield. These force the circuit designer to employ EDA tools, particularly timing signoff, to strike a delicate balance. Tempering the designer's zeal are the above-described process and environmental variations to which every production circuit is subject. These variations increase the degree to which the designer must ensure that production circuits work under real-world operating conditions and therefore the complexity of timing signoff.
Further complicating the designer's task is the difficulty of measuring and therefore being able to judge tradeoffs of speed and power consumption. Some metrics are effective for one process technology, but fail to translate to other technologies. Other metrics may apply to multiple technologies, but are difficult to understand and defy intuition. Thus, a designer is left with having to optimize based on experience and trust that he can communicate the wisdom of his decisions.